The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
May. 22, 2017
Applicant:
Sony Corporation, Tokyo, JP;
Inventor:
Jun Sumino, Boise, ID (US);
Assignee:
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 27/115 (2017.01); H01L 27/11524 (2017.01); H01L 27/11548 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 23/528 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract
Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.