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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10050019 B1

PDFFull Text
Date of Patent:
Aug. 14, 2018

Filed:

Jan. 13, 2017

Method of manufacturing wafer level package and wafer level package manufactured thereby

Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Tae Hoon Kim, Icheon-si, KR;

Jong Hoon Kim, Suwon-si, KR;

Dae Won Kim, Icheon-si, KR;

Hyeong Seok Choi, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:

William Park & Associates Ltd.

Primary Examiner:

Brook Kebede

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/295 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/07025 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1443 (2013.01);
Abstract

Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

Find Patent Forward Citations

Kim, Tae. (2018). Method of manufacturing wafer level package and wafer level package manufactured thereby (U.S. Patent No. 10050019). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10050019

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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