The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

May. 16, 2017
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Christian Rivero, Rousset, FR;

Pascal Fornara, Pourrieres, FR;

Guilhem Bouton, Peynier, FR;

Mathieu Lisart, Aix en Provence, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/7685 (2013.01); H01L 21/76804 (2013.01); H01L 21/76883 (2013.01); H01L 21/76892 (2013.01); H01L 23/5226 (2013.01);
Abstract

An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.


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