The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Jul. 06, 2015
Applicants:

Massachusetts Institute of Technology, Cambridge, MA (US);

Nanyang Technological University, Singapore, SG;

Inventors:

Kwang Hong Lee, Singapore, SG;

Chuan Seng Tan, Singapore, SG;

Eugene A. Fitzgerald, Cambridge, MA (US);

Eng Kian Kenneth Lee, Singapore, SG;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/8258 (2006.01); H01L 27/092 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/0217 (2013.01); H01L 21/30612 (2013.01); H01L 21/76251 (2013.01); H01L 27/0635 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01);
Abstract

A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.


Find Patent Forward Citations

Loading…