The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
May. 04, 2016
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventors:
Chang Hyun Lee, Icheon-si, KR;
Young Jun Ku, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3181 (2006.01); G11C 29/08 (2006.01); G11C 29/12 (2006.01); G11C 29/26 (2006.01); G11C 29/46 (2006.01); G11C 29/50 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12015 (2013.01); G01R 31/3181 (2013.01); G11C 29/08 (2013.01); G11C 29/26 (2013.01); G11C 29/46 (2013.01); G11C 29/50012 (2013.01); G11C 29/1201 (2013.01); G11C 2029/2602 (2013.01); G11C 2029/5602 (2013.01);
Abstract
A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.