The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Aug. 06, 2015
Applicants:

Japan Science and Technology Agency, Kawaguchi-shi, Saitama, JP;

Kanagawa Academy of Science and Technology, Kawasaki-shi, Kanagawa, JP;

Inventors:

Satoshi Sugahara, Yokohama, JP;

Yusuke Shuto, Yokohama, JP;

Shuichiro Yamamoto, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); G11C 11/419 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0081 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 11/419 (2013.01);
Abstract

A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.


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