The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Oct. 13, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yang Liu, Shanghai, CN;

Yue Xu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 17/50 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3237 (2013.01); G06F 1/12 (2013.01); G06F 1/3234 (2013.01); G06F 17/5036 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01);
Abstract

Power consumption of an integrated circuit (IC) clock mesh can be managed by a method of clock mesh design. Clock mesh data, including a location of a set of circuit elements and gating information of the set of circuit elements of the clock mesh, can be retrieved. A portion of the clock mesh, known as a local clock mesh, can be identified by analyzing the clock mesh data. The local clock mesh can include a subset of circuit elements having substantially similar clock gating characteristics, and which satisfy a placement density threshold. Mesh clock gating (MCG) cells can be added to wires surrounding the perimeter of the local mesh. MCG cells can be configured to enable and disable clock loads and clock mesh wires within the local clock mesh.


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