The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Sep. 09, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hans-Peter Moll, Dresden, DE;

Uwe Dersch, Dresden, DE;

Ricardo Pablo Mikalo, Heideblick, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01); G01R 31/26 (2014.01); H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2621 (2013.01); H01L 27/1203 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/42376 (2013.01); G01R 31/2884 (2013.01);
Abstract

A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.


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