The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
Mar. 02, 2015
Altera Corporation, San Jose, CA (US);
Srikanth Darbha, San Jose, CA (US);
Ronald M. Beach, Pleasanton, CA (US);
Vadali Mahadev, San Jose, CA (US);
Ganesh Sure, Cupertino, CA (US);
Kaushik Chanda, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A test system for testing an integrated circuit package is provided. The test system may include a test board on which a package under test can be mounted, a test box for gathering desired measurements on the package under test, and a test host for automatically controlling the test box during testing. The test box may be coupled to row multiplexing circuitry and column multiplexing circuitry for selectively addressing one or more daisy-chained nets in the package under test. The test box may also be coupled to a source measurement unit (SMU) component that provides current source signals to the package under test and to a digital multimeter (DMM) component that provides voltage sense signals to the package under test. Arranged in this way, the test system can be configured to perform automated I-V curve tracing, resistance measurements, open/short circuit detection, and monitoring of other package-level manufacturing defects.