The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jul. 13, 2015
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Rajneesh Mishra, Vaishali, IN;

Brett Caldwell, Nepean, CA;

Mohit Batra, Derawal Nagar, IN;

Tajeshwar Gill, Haryana, IN;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/703 (2013.01); H04L 12/721 (2013.01); H04L 12/939 (2013.01); H04L 12/26 (2006.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 45/28 (2013.01); H04L 43/0805 (2013.01); H04L 45/66 (2013.01); H04L 49/557 (2013.01); H04L 41/145 (2013.01);
Abstract

A node configured to emulate a hardware UP Maintenance End Point (MEP) using one or more DOWN MEPs includes a plurality of ports; a switching fabric configured to switch data between the plurality of ports; and processing circuitry communicatively coupled to the plurality of ports and configured to emulate an UP MEP on a first port of the plurality of ports using at least a first DOWN MEP on a second port of the plurality of ports. The DOWN MEP can be implemented in hardware on the second port and the processing circuitry can be configured to execute application software configured to emulate the UP MEP.


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