The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jul. 31, 2017
Applicant:

Saturn Licensing Llc, New York, NY (US);

Inventors:

Jean-Luc Peron, Suresnes, FR;

Matthew Paul Athol Taylor, Ringwood, GB;

John Nicholas Wilson, Hook, GB;

Samuel Asangbeng Atungsiri, Basingstoke, GB;

Assignee:

SATURN LICENSING LLC, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04K 1/10 (2006.01); H04L 27/26 (2006.01); H03M 13/27 (2006.01); H04L 5/00 (2006.01); H03M 13/00 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 27/2602 (2013.01); H03M 13/2742 (2013.01); H03M 13/6552 (2013.01); H04L 1/0071 (2013.01); H04L 5/0007 (2013.01); H04L 5/0044 (2013.01); H04L 5/0048 (2013.01); H04L 27/2626 (2013.01); H04L 27/2646 (2013.01); H04L 1/0057 (2013.01); H04L 27/2601 (2013.01);
Abstract

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.


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