The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Mar. 21, 2014
Applicant:

Empire Technology Development Llc, Wilmington, DE (US);

Inventor:

Nagi Mekhiel, Markham, CA;

Assignee:

Empire Technology Development LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G06F 1/04 (2006.01); H03K 5/15 (2006.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0091 (2013.01); G06F 1/04 (2013.01); H03K 5/15066 (2013.01); H04L 7/0008 (2013.01); H04L 12/4013 (2013.01);
Abstract

Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.


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