The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

May. 19, 2017
Applicant:

Analog Devices Global, Hamilton, BM;

Inventors:

Hanqing Wang, Beijing, CN;

Gerard Mora-Puchalt, Catarroja, ES;

Assignee:

Analog Devices Global, Hamilton, BM;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/00 (2006.01); H03F 1/02 (2006.01); H03F 1/32 (2006.01); H03F 1/56 (2006.01); H03F 3/393 (2006.01); H03F 3/42 (2006.01); H03F 3/45 (2006.01); H03F 1/14 (2006.01); H03F 3/387 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03F 3/005 (2013.01); H03F 1/02 (2013.01); H03F 1/14 (2013.01); H03F 1/3211 (2013.01); H03F 1/56 (2013.01); H03F 3/387 (2013.01); H03F 3/393 (2013.01); H03F 3/426 (2013.01); H03F 3/45071 (2013.01); H03F 3/45475 (2013.01); H03M 3/00 (2013.01); H03F 2200/213 (2013.01); H03F 2200/267 (2013.01); H03F 2200/271 (2013.01); H03F 2200/378 (2013.01); H03F 2203/45458 (2013.01); H03F 2203/45514 (2013.01);
Abstract

A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.


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