The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Sep. 12, 2017
Applicant:

Dialog Semiconductor (Uk) Limited, London, GB;

Inventors:

Mark Childs, Swindon, GB;

Michele DeFazio, Germering, DE;

Carsten Barth, Schwaebisch Gmuend, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/157 (2006.01); H02M 3/158 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/157 (2013.01); H02M 3/1588 (2013.01); H02M 2001/0009 (2013.01); H02M 2001/0025 (2013.01);
Abstract

The proposed disclosure combines peak-mode monitoring with valley-mode control, in a Buck switching converter, by means of a peak-current sampling circuit, not to turn the high side device off, but to control a slow loop, which in turn controls a variable offset incorporated into the loop control current. This helps the loop control current define the exact peak current, regardless of what other offsets, compensation ramp or peak-to-peak current ripple, are applied to the loop control current. The peak current is determined by an operational transconductance amplifier (OTA), whose maximum current is clamped to a programmed value. The loop control current is most likely implemented using a digital successive approximation register (SAR) system, but may also be implemented using a slow analog control loop.


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