The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jul. 18, 2016
Applicants:

Tae-hee Lee, Suwon-si, KR;

Hong-soo Kim, Seongnam-si, KR;

Kyoung-hoon Kim, Seoul, KR;

Young-suk Lee, Daejeon, KR;

Inventors:

Tae-Hee Lee, Suwon-si, KR;

Hong-Soo Kim, Seongnam-si, KR;

Kyoung-Hoon Kim, Seoul, KR;

Young-Suk Lee, Daejeon, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); G11C 16/08 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01);
Abstract

A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.


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