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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10043798 B1

PDFFull Text
Date of Patent:
Aug. 07, 2018

Filed:

Aug. 25, 2016

Buried interconnect for semiconductor circuits

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Stefan Cosemans, Mol, BE;

Praveen Raghavan, Bertem, BE;

Steven Demuynck, Aarschot, BE;

Julien Ryckaert, Tervuren, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

Knobbe Martens Olson & Bear, LLP

Primary Examiner:

Kimberly Rizkallah

Assistant Examiner:

Bo Bin Jang

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/743 (2013.01); H01L 21/76895 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

Find Patent Forward Citations

Cosemans, Stefan. (2018). Buried interconnect for semiconductor circuits (U.S. Patent No. 10043798). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10043798

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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