The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2018
Filed:
Mar. 09, 2017
Applicant:
Youngbae Kim, Seoul, KR;
Inventor:
Youngbae Kim, Seoul, KR;
Assignee:
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17135 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33134 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3512 (2013.01);
Abstract
A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first substrate, a second substrate on the lower package, interconnect terminals between the first substrate and the second substrate, and an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern extends along an edge of the semiconductor chip. The adhesive pattern exposes a top surface of a central zone of the semiconductor chip.