The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Apr. 17, 2017
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sang Kyu Lee, Suwon-si, KR;

Jin Gu Kim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 23/3128 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/13024 (2013.01);
Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.


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