The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Aug. 29, 2017
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ji Hyun Lee, Suwon-si, KR;

Hyoung Joon Kim, Suwon-si, KR;

Kyoung Moo Harr, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 23/3114 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19106 (2013.01);
Abstract

A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.


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