The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jun. 26, 2015
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takafumi Betsui, Kodaira, JP;

Motoo Suwa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 23/538 (2006.01); H01L 23/50 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 23/538 (2013.01); H01L 23/50 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01);
Abstract

An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip. An area of a region of the first power supply line, the region overlapping with the second power supply line in a thickness direction, is smaller than an area of another region of the first power supply line, the another region not overlapping with the second power supply line.


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