The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jul. 02, 2017
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Tomohiko Aika, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/762 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); G03F 7/16 (2006.01); G03F 7/24 (2006.01); G03F 7/09 (2006.01); G03F 7/11 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); G03F 7/094 (2013.01); G03F 7/11 (2013.01); G03F 7/162 (2013.01); G03F 7/24 (2013.01); H01L 21/0273 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 29/0649 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm, in a process for patterning a silicon oxide film which will serve as a hard mask. A part of the silicon oxide film which is positioned in the outer circumferential region is removed, thereby exposing the semiconductor substrate, in a process for performing an etching process for patterning the silicon oxide film. In the process for performing the etching process for the semiconductor substrate with using the silicon oxide film as an etching mask, the surface of the semiconductor substrate of the outer circumferential region is lowered. Then, a step difference is formed in a position nearer to a chip formation region, in the semiconductor substrate.


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