The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Nov. 19, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Gangadhar Budde, Latur, IN;

Pradeep Kumar Mishra, Hyderabad, IN;

Somdutt Javre, Seoni, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 21/62 (2013.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/6218 (2013.01); G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01);
Abstract

Methods and systems are disclosed for determining mask-value pairs for controlling access to a memory segment for a plurality of IDs. A first set of mask-value pairs is determined for a set of allowed identifiers (IDs) and a set of non-allowed IDs. Each mask-value pair of the first set matches at least one ID of the set of allowed IDs and does not match any of the IDs of the set of non-allowed IDs. Redundant mask-value pairs are removed from the first set to produce a second set. Subsets of mask-value pairs in the second set that match the entire set of allowed IDs are determined. The subset having the highest processing efficiency is determined and selected. A set of configuration data is generated that is configured to cause a memory management circuit to enforce access to the memory segment based on the selected subset of mask-value pairs.


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