The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Mar. 30, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Assaf Shacham, Zichron Yaakov, IL;

Shaul Yohai Yifrach, Haifa, IL;

Thomas Zeng, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1027 (2016.01); G06F 3/06 (2006.01); G06F 12/1081 (2016.01); G06F 13/28 (2006.01); G06F 12/0891 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/1081 (2013.01); G06F 13/28 (2013.01); G06F 12/0891 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/683 (2013.01); Y02D 10/13 (2018.01);
Abstract

Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.


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