The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Nov. 07, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Sang-Jin Byeon, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 7/10 (2006.01); G11C 29/52 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 5/02 (2013.01); G11C 7/10 (2013.01); G11C 29/52 (2013.01);
Abstract

A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.


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