The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2018
Filed:
Aug. 22, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Venkat Narayanan, San Diego, CA (US);
Qi Ye, San Diego, CA (US);
Manish Srivastava, Bangalore, IN;
Venugopal Boynapalli, San Marcos, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); H03K 3/013 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); H03K 3/013 (2013.01); H03K 3/356139 (2013.01);
Abstract
A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.
Narayanan, Venkat. (2018). High-speed soft-edge sense-amplifier-based flip-flop (U.S. Patent No. 10038429). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10038429
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile