The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Dec. 13, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

See Taur Lee, Allen, TX (US);

Abdellatif Bellaouar, Richardson, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/34 (2006.01); H03F 1/52 (2006.01); H03F 1/22 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01); H03F 3/45 (2006.01); H03F 3/30 (2006.01); H03F 1/30 (2006.01);
U.S. Cl.
CPC ...
H03F 1/523 (2013.01); H03F 1/223 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03F 3/45179 (2013.01); H03F 1/22 (2013.01); H03F 1/307 (2013.01); H03F 3/3022 (2013.01); H03F 3/45 (2013.01); H03F 3/45071 (2013.01); H03F 3/45183 (2013.01); H03F 2200/171 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45154 (2013.01); H03F 2203/45202 (2013.01); H03F 2203/45228 (2013.01); H03F 2203/45462 (2013.01);
Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.


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