The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2018
Filed:
Dec. 19, 2014
Alpes Lasers SA, St-Blaise, CH;
Richard Maulini, Marin-Epagnier, CH;
Alfred Bismuto, San Jose, CA (US);
Tobias Gresch, Lausanne, CH;
Antoine Müller, Neuchatel, CH;
Alpes Lasers SA, St-Blaise, CH;
Abstract
For epitaxial-side-down bonding of quantum cascade lasers (QCLs), it is important to optimize the heat transfer between the QCL chip and the heat sink to which the chip is mounted. This is achieved by using a heatsink with high thermal conductivity and by minimizing the thermal resistance between the laser active region and said heatsink. In the epi-down configuration concerned, the active region of the QCL is located only a few micrometers away from the heatsink, which is preferable from a thermal standpoint. However, this design is challenging to implement and often results in a low fabrication yield if no special precautions are taken. Since the active region is very close to the heatsink, solder material may ooze out on the sides of the chip during the bonding process and may short-circuits the device, rendering it unusable. To avoid this happening, the invention proposes to provide a trench all around the chip with the exception of the two waveguide facets, i.e. the ends of the active region. This trench may be etched into the otherwise standard QCL chip or otherwise machined into the chip, providing an initially empty space for the volume of solder displaced by the chip during the epi-down bonding process, which empty space is occupied by the surplus solder without contacting the side of the chip and thus short-circuiting the device.