The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Nov. 07, 2014
Applicant:

Sakai Display Products Corporation, Sakai-shi, Osaka, JP;

Inventors:

Nobutake Nodera, Sakai, JP;

Shigeru Ishida, Sakai, JP;

Ryohei Takakura, Sakai, JP;

Yoshiaki Matsushima, Sakai, JP;

Takao Matsumoto, Sakai, JP;

Kazuki Kobayashi, Sakai, JP;

Taimi Oketani, Sakai, JP;

Assignee:

Sakai Display Products Corporation, Sakai-shi, Osaka, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78663 (2013.01); G02F 1/136277 (2013.01); G02F 2001/136295 (2013.01);
Abstract

The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.


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