The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

May. 19, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yong Ju Lee, San Diego, CA (US);

Yang Du, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 23/535 (2006.01); H01L 21/04 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1606 (2013.01); H01L 21/0272 (2013.01); H01L 21/0273 (2013.01); H01L 21/02112 (2013.01); H01L 21/02378 (2013.01); H01L 21/02527 (2013.01); H01L 21/044 (2013.01); H01L 23/535 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66045 (2013.01); H01L 29/6653 (2013.01); H01L 29/66742 (2013.01); H01L 29/78684 (2013.01);
Abstract

An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NOlayer formed on the graphene channel, a high-k dielectric formed over the adsorbed NOlayer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NOlayer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (V) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.


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