The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Jul. 07, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Yoshinori Kaya, Ibaraki, JP;

Yasushi Nakahara, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H03K 3/356 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1087 (2013.01); H01L 29/063 (2013.01); H01L 29/0623 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/7823 (2013.01); H03K 3/356 (2013.01); H03K 17/06 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01); H03K 2217/0081 (2013.01);
Abstract

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n-type semiconductor region which surrounds the coupling transistor in plan view.


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