The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

May. 29, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jason Edward Podaima, Toronto, CA;

Paul Christopher John Wiercienski, Toronto, CA;

Kyle John Ernewein, Toronto, CA;

Carlos Javier Moreira, Markham, CA;

Meghal Varia, Brampton, CA;

Serag Gadelrab, Markham, CA;

Muhammad Umar Choudry, Markham, CA;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/0862 (2016.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 12/10 (2013.01); G06F 12/109 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/283 (2013.01); G06F 2212/312 (2013.01); G06F 2212/507 (2013.01); G06F 2212/608 (2013.01); G06F 2212/6026 (2013.01); G06F 2212/65 (2013.01); G06F 2212/654 (2013.01);
Abstract

Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.


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