The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Sep. 09, 2014
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Cristian Mitrea, San Pedro, CA (US);

Herbert Zojer, Torrance, CA (US);

Benjamim Tang, Rancho Palos Verdes, CA (US);

Bessegato Renato, Oberhaching, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); H02M 3/157 (2006.01); G06F 1/32 (2006.01); G06F 13/38 (2006.01); H02M 3/155 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/3293 (2013.01); G06F 13/38 (2013.01); G06F 1/26 (2013.01); H02M 3/155 (2013.01); H02M 3/157 (2013.01);
Abstract

A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.


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