The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Apr. 15, 2016
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zuqiang Wang, Beijing, CN;

Guang Li, Beijing, CN;

Liang Sun, Beijing, CN;

Xiaoyong Lu, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/13 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); H01L 27/32 (2006.01); G01R 31/28 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1309 (2013.01); G01R 31/2825 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/136286 (2013.01); H01L 27/3262 (2013.01); G02F 2001/136254 (2013.01); G02F 2001/136295 (2013.01); H01L 2227/323 (2013.01);
Abstract

A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.


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