The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Sep. 29, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Masaaki Higuchi, Yokohama Kanagawa, JP;

Masao Shingu, Yokkaichi Mie, JP;

Tatsuya Kato, Yokkaichi Mie, JP;

Takeshi Murata, Yokkaichi Mie, JP;

Makoto Fujiwara, Yokkaichi Mie, JP;

Masaki Kondo, Yokkaichi Mie, JP;

Muneyuki Tsuda, Ichinomiya Aichi, JP;

Takashi Kurusu, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7923 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 29/1037 (2013.01);
Abstract

A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.


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