The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

May. 19, 2016
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventors:

Yanxi Ye, Shenzhen, CN;

Yunglun Lin, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/51 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); G02F 1/1345 (2006.01); G02F 1/1368 (2006.01); H01L 21/768 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G02F 1/1345 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 21/31111 (2013.01); H01L 21/32134 (2013.01); H01L 21/76802 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 27/1248 (2013.01); H01L 27/1288 (2013.01); H01L 29/518 (2013.01); G02F 2001/136295 (2013.01);
Abstract

The present invention provides a method for bonding pins in OLB area, by forming via holes on the planarization layer of the OLB area corresponding to each pin, the subsequently formed connection wires connecting the pins through the via holes above the pins so that the corresponding pins being connected by the connection wires. As the connection wires completely cover the via holes above the pins, the problem of residual conductive material in the via holes during forming the connection wires does not occur. Compared to the known technology opening a large area on the planarization layer of the OLB area, the present invention avoids the conductive material residual at the bottom of the via hole on the planarization layer and related short circuit and poor display problems.


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