The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Nov. 04, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-Do, KR;

Inventors:

Zhu Xun, Suwon-si, KR;

Jae Woo Park, Seongnam-si, KR;

Jae Won Song, Seoul, KR;

Keum Hee Lee, Goyang-si, KR;

June Whan Choi, Hwaseong-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/00 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 21/443 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); G02F 1/1335 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 21/443 (2013.01); H01L 21/76852 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 29/41733 (2013.01); H01L 29/458 (2013.01); H01L 29/66765 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); G02F 1/1368 (2013.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G02F 2001/133519 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); H01L 23/53238 (2013.01); H01L 27/1288 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.


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