The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Jun. 21, 2017
Applicants:

Smart Modular Technologies Lx S.a.r.l, Seongnam-si, Gyeonggi-do, KR;

Bum Wook Park, Seoul, KR;

Hyun Jung, Seoul, KR;

Inventors:

Bum Wook Park, Seoul, KR;

Hyun Jung, Seoul, KR;

Assignee:

SMART MODULAR TECHNOLOGIES LX S.A.R.L., Seongnam-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/1401 (2013.01); H01L 2224/14517 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01029 (2013.01);
Abstract

The present invention provides a method for forming bumps of a semiconductor package to suppress a final height difference between main bumps and support bumps that is caused by a height difference between areas of an underlying layer when viewed on a cross-section. The method may include forming first seed layer patterns and second seed layer patterns which are disposed in the areas and are separated from each other, over the underlying layer having the height difference. The method may include forming the main bumps and the support bumps of which final heights are the same when viewed on the cross-section in the areas, by performing electroplating through using, as electrodes, the first seed layer patterns and the second seed layer patterns which are disposed in the areas and are separated from each other, under different conditions in the areas.


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