The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2018
Filed:
Sep. 23, 2014
Applicant:
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Inventors:
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 29/778 (2006.01); H01L 27/06 (2006.01); H01L 27/085 (2006.01); H01L 23/482 (2006.01); H01L 23/495 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 23/4824 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 27/0207 (2013.01); H01L 27/0605 (2013.01); H01L 27/085 (2013.01); H01L 27/088 (2013.01); H01L 29/7787 (2013.01); H01L 29/2003 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/0605 (2013.01); H01L 2224/091 (2013.01); H01L 2224/45014 (2013.01); H01L 2224/4846 (2013.01); H01L 2224/4847 (2013.01); H01L 2224/48096 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/49431 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10161 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30101 (2013.01);
Abstract
A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.