The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Feb. 19, 2016
Applicant:

Google Inc., Mountain View, CA (US);

Inventors:

Madhu Krishnan Iyengar, Foster City, CA (US);

Teck-Gyu Kang, Saratoga, CA (US);

Christopher Gregory Malone, Mountain View, CA (US);

Norman Paul Jouppi, Palo Alto, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 23/04 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2006.01); H01L 23/44 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 23/04 (2013.01); H01L 23/3675 (2013.01); H01L 23/3732 (2013.01); H01L 23/3736 (2013.01); H01L 23/3737 (2013.01); H01L 23/44 (2013.01); H01L 23/498 (2013.01); H01L 25/18 (2013.01); H01L 25/0652 (2013.01);
Abstract

A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.


Find Patent Forward Citations

Iyengar, Madhu. (2018). Powermap optimized thermally aware 3d chip package (U.S. Patent No. 10032695). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10032695

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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