The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Mar. 20, 2018
Applicant:

Uniquify Ip Company, Llc, San Francisco, CA (US);

Inventors:

Mahesh Gopalan, Milpitas, CA (US);

David Wu, Saratoga, CA (US);

Venkat Iyer, Sunnyvale, CA (US);

Assignee:

Uniquify IP Company, LLC, San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4076 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G11C 7/22 (2006.01); G06F 12/06 (2006.01); G06F 1/14 (2006.01); G06F 1/12 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); G06F 3/0619 (2013.01); G06F 12/0646 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/4093 (2013.01);
Abstract

A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.


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