Verification of untimed nets

Abstract

Integrated circuits (ICs) rely on static timing analysis during their design to ensure that they will operate at desired frequencies. Delays between sequential elements (e.g., latches and flip-flops) are constrained to meet target clock periods. Certain signals, however, such as untimed nets may be excluded from timing constraints if the circuit function does not require these nets to switch and propagate to sequential elements within the clock period. However, a signal marked as 'untimed' may have been mistakenly specified by the designer as an untimed net. To verify that an untimed net does not negatively impact the function of the design logic, the embodiments herein generate upstream and downstream event networks using shadow logic that corresponds to design logic upstream and downstream of the untimed net. A metastability network coupled to these networks is used to model nondeterminism and metastability resulting from transitions or potential glitches on the untimed net.