The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
Jul. 09, 2015
Broadcom Corporation, Irvine, CA (US);
Chung Ming Tu, Irvine, CA (US);
Peiqing Wang, Laguna Beach, CA (US);
Ahmad Chini, Mission Viejo, CA (US);
Yencheng Chen, Fremont, CA (US);
Mehmet Vakif Tazebay, Irvine, CA (US);
Bazhong Shen, Irvine, CA (US);
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., Singapore, SG;
Abstract
A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.