Method of digital-to-analog converter mismatch calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

Abstract

A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V), detecting if a binary code determined from the analog input signal (V) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*) and a calibration bit (B*), analyzing a least significant bit of the digital signal (C) and the calibration bit (B*), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.