The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Mar. 14, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Albert Birner, Regensburg, DE;

Helmut Brech, Lappersdorf, DE;

Matthias Zigldrum, Regensburg, DE;

Michaela Braun, Regensburg, DE;

Christian Eckl, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/768 (2006.01); H03F 3/193 (2006.01); H03F 1/02 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 21/76898 (2013.01); H01L 29/402 (2013.01); H01L 29/7823 (2013.01); H03F 1/0288 (2013.01); H03F 3/193 (2013.01); H03F 2200/451 (2013.01);
Abstract

In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.


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