The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Nov. 11, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Jinwoo Park, Gunpo-si, KR;

Jaeshin Park, Hwaseong-si, KR;

Joyoung Park, Seoul, KR;

Jiwoong Sue, Yongin-si, KR;

Seok-Won Lee, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76879 (2013.01); H01L 23/5283 (2013.01); H01L 27/0207 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.


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