The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Nov. 23, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Andi Zhao, San Diego, CA (US);

Ramaprasath Vilangudipitchai, San Diego, CA (US);

Dorav Kumar, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 23/528 (2013.01); H01L 23/5222 (2013.01); H01L 27/0207 (2013.01); H03K 17/162 (2013.01);
Abstract

A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.


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