The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
Feb. 27, 2017
Samsung Electronics Co., Ltd., Suwon-si, KR;
Ji-hwang Kim, Cheonan-si, KR;
Jong-bo Shim, Asan-si, KR;
Sang-uk Han, Hwaseong-si, KR;
Cha-jea Jo, Yongin-si, KR;
Gun-ho Chang, Yongin-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongton-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.