The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

May. 25, 2016
Applicant:

Broadpak Corporation, San Jose, CA (US);

Inventor:

Farhang Yazdani, Santa Clara, CA (US);

Assignee:

BroadPak Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 25/10 (2006.01); H01L 23/04 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/13 (2006.01); H01L 23/36 (2006.01); H01L 23/467 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/486 (2013.01); H01L 21/52 (2013.01); H01L 23/04 (2013.01); H01L 23/13 (2013.01); H01L 23/3107 (2013.01); H01L 23/36 (2013.01); H01L 23/467 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/573 (2013.01); H01L 23/66 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1082 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/30107 (2013.01); Y10T 29/53174 (2015.01); Y10T 29/53178 (2015.01); Y10T 29/53183 (2015.01);
Abstract

An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.


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