The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

May. 17, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Kenichiro Sonoda, Tokyo, JP;

Eiji Tsukuda, Tokyo, JP;

Keiichi Maekawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/10 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/06 (2006.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/0649 (2013.01); H01L 29/792 (2013.01); G11C 16/3418 (2013.01);
Abstract

A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.


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