The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Feb. 01, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Sung-Jae Yun, Hwaseong-si, KR;

Dong Han Song, Hwaseong-si, KR;

Ki Chul Shin, Seongnam-si, KR;

Hyeok Jin Lee, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G09G 3/36 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1337 (2006.01);
U.S. Cl.
CPC ...
G09G 3/36 (2013.01); G02F 1/1337 (2013.01); G02F 1/133305 (2013.01); G02F 1/134309 (2013.01); G02F 1/134336 (2013.01); G02F 1/136213 (2013.01); G02F 1/136286 (2013.01); G09G 3/3655 (2013.01); G02F 2001/133742 (2013.01); G02F 2201/12 (2013.01); G09G 2380/02 (2013.01);
Abstract

A liquid crystal display having a curved surface includes: a display panel including a first display panel, a second display panel, and a liquid crystal layer interposed therebetween and including liquid crystal molecules. The first display panel includes a first substrate on which a plurality of gate lines and data lines are formed, a first electrode, and a pixel electrode. The second display panel includes a second substrate facing the first substrate and a second electrode. The liquid crystal display further includes a common voltage supplier applying two voltages having a predetermined voltage difference to the first and second electrodes within a period before a frame displaying an image on the display panel; a gate driver applying a gate signal to each of the gate lines after the period; and a data driver applying a data voltage to the pixel electrode corresponding to the gate signal.


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